INTEL 6 Motherboard Series Power Timing

INTEL 6 Motherboard Series Power Timing

INTEL 6 series Power Timing

INTEL 6 series chipset, is a relatively new chipset, now has some colleagues began

Access repair, because the 6 series chipset is relatively new, so with a lot of new technology, the circuit is relatively complex

Miscellaneous some, but also some more new signal today for six series and signal timing to make a Detailed,

Help us in maintenance when 6 series chipset can be more handy.

First look at the official white paper INTEL 6 series chipset S5-S0 state timing, but also

A process is a normal board power until the CPU work.

First look at the white paper to see how the standard timing, the top three options, Source is the source

Head mean, here representing the equipment issued, Dest is the meaning of destination, sent here to represent

What equipment, Signal Name is the name of the signal, this is the process that each timing signal

It is called, to help us check in the circuit diagram.

1, SLP_S5 #

This signal is the timing of the first working signal, under normal circumstances it should be generated when the board has power,

Is generated by the EC and sent to KB930QF Zheke PCH, under normal circumstances, this signal should be high.

2, SLP_S4 #

This signal is in entering the ACPI S4 (hibernation, the data is written to the hard disk) signal status only

When the board is in hibernation, this signal will be low, under normal circumstances, this signal should also

High level. (General motherboard designs, after the exclusion of hibernation, SLP_S5 # and SLP_S4 # can

As the same signal to)

3, SLP_S3 #

This signal is in entering the ACPI S3 (sleep, data is written to memory) signal state, which

Signal is more important, when the board is pressing the power switch, power switch will give an open EC

Signal received after the EC, through the internal logic processing, will release a PBTN_OUT # signal to the Southbridge,

Southbridge After receiving this signal, the other working conditions were normal after Southbridge, after an internal logic, will according to

Second release SLP_S5 #, SLP_S4 #, SLP_S3 # to EC, in the traditional INTEL platform, this

SLP_S3 # signal is a sign of the signal, after the signal is valid, EC will issue a turn on the power to do

Pressure preparation signal.

4, SLP_A #

This signal is a new enlargement of the signal that is used to open the PCH PCH in Active

Sleep Well (active sleep circuit, referred to as ASW circuit) which comes from the Intel Management

Engine technology and INTEL Active Management Technology technology, the INTEL management

Engine Technology (ME technology) and INTEL Active Management Technology (AMT technology) in the two new technologies

Support, with specialized software, you can use the Internet to carry out the management of the computer. SLP_A # in

After the ME circuit PCH partially powered and effective after goes high.

It has a high level, that is to say the signal is required by the different designs of this signal is possible prior to: PS

To configure, but the signal will never be effective in SLP_S3 # after.

5, SLP_LAN #

This signal is an enlargement of a new signal that is SLP_A # signal with the presence of the

To support the ME in technology, so PCH must Ethernet module for external control power to

Technical support will be completed by the AMT software on a computer via Ethernet to enable or disable purposes.

When the motherboard can normally energized, SLP_A # and SLP_LAN # must be high.

PS: This signal is also possible before it has been in the high voltage state (wake up in support WOL network

Case), but the signal will never be effective in SLP_S3 # after.

When all the signals are high the SLP, EC turn sends a voltage signal to open the S0 voltage,

That is RUN voltage.

6, VccASW

This voltage is a supply of new zo is powered ASW work, the voltage is 1.05V,

This voltage is AMT module and card modules supply.

7, VCC

Other power supply VCC here for PCH need.

8, CPU_SVID

CPU_SVID is a set of signal CPU VRM power chips issued by the CPU, and the DATA

Standard serial bus, and a prompt action from the ALERT # signal CLK composed of the composition.

9, VccCore_CPU

This is well understood, the CPU power is determined by a combination of power IC received CPU_SVID signal, press

Predetermined information sent to the CPU operating voltage.

10, SYS_PWROK

This signal is the CPU VRM chip CPU VCORE voltage has stabilized and stabilized sent to PCH

Power good tips signal that indicate CPU VCORE power supply is normal.

11, PWROK

When the main voltages are effective and stable, it will emit a signal to PWROK PCH (usually by

EC monitoring voltage and emit the signal), notify the brightest RUN PCH voltages are ready.

12, APWROK

This signal is also a new enlargement of the signal, usually after ASW powered by EC monitoring effective and stable,

Send to PCH, show ASW module power supply stable.

13, DRAMPWROK

This signal is an enlargement of the new signal, the signal pin and CPU SM_DRAMPWROK

Connected, PCH asserts this signal to indicate DRAM (memory) voltage is stable.

14,25MHz

This frequency is sent to the PCH 25MHz crystal oscillator frequencies, providing work for PCH internal clock module

For the desired reference frequency.

15, PCH OutPut CLOCKS

PCH internal clock module in the operating conditions are met, will be issued on the motherboard other equipment required for a

Series of clock frequency.

16, PROCPWRGD

This signal is sent from the PCH, the pin is sent to the CPU UNCOREPWRGOOD Table

That the CPU power supply is stable.

PS: When PRCOPWRGD effective, CPU can IMVP7 specification to adjust the voltage according to power

Festival voltage, namely low ALERT # signal and then re-issued a set of SVID signal. And restart 8-16

Cycling steps.

17, SUS_STAT #

This signal indicates that the system enters a suspended state, the signal from the PCH claims system into a low power state,

This signal can also be used for other peripheral devices to turn off the output. This signal should be in the normal starting process

Driven high.

18, THRMTRIP #

This signal is a signal for monitoring the core temperature of the CPU, when the monitored temperature rises to the limit to

After time, THRMTRIP # signal is driven low, PCH receive THRMTRIP # signal, it will immediately

Drive SLP_S5 # signal is low, so that the whole system into the S5 state, close supply. Also known

Said temperature causes power failure.

PS: Before PRCOPWRGD effective, THRMTRIP # signal is negligible. Only in

After PRCOPWRGD effective, THRMTRIP # before they can work. This signal is high under normal

Flat, and only when the CPU temperature is too high may be driven low.

19, PLTRST #

This signal is always reset the entire platform, when SUS_STAT # is driven high 60US

After, PLTRST # is driven high. Complete reset of the other devices and the CPU.

20, DMI

After PLTRST # is driven high, CPU and PCH via DMI bus for data exchange,

Complete the boot process. Overall timing of the end.

composition.9, VccCore_CPUThis is well understood, the CPU power is determined by a combination of power IC received CPU_SVID signal, pressPredetermined information sent to the CPU operating voltage.10, SYS_PWROKThis signal is the CPU VRM chip CPU VCORE voltage has stabilized and stabilized sent to PCHPower good tips signal that indicate CPU VCORE power supply is normal.11, PWROKWhen the main voltages are effective and stable, it will emit a signal to PWROK PCH (usually byEC monitoring voltage and emit the signal), notify the brightest RUN PCH voltages are ready.12, APWROKThis signal is also a new enlargement of the signal, usually after ASW powered by EC monitoring effective and stable,Send to PCH, show ASW module power supply stable.13, DRAMPWROKThis signal is an enlargement of the new signal, the signal pin and CPU SM_DRAMPWROKConnected, PCH asserts this signal to indicate DRAM (memory) voltage is stable.14,25MHzThis frequency is sent to the PCH 25MHz crystal oscillator frequencies, providing work for PCH internal clock moduleFor the desired reference frequency.15, PCH OutPut CLOCKSPCH internal clock module in the operating conditions are met, will be issued on the motherboard other equipment required for aSeries of clock frequency.16, PROCPWRGDThis signal is sent from the PCH, the pin is sent to the CPU UNCOREPWRGOOD TableThat the CPU power supply is stable.PS: When PRCOPWRGD effective, CPU can IMVP7 specification to adjust the voltage according to powerFestival voltage, namely low ALERT # signal and then re-issued a set of SVID signal. And restart 8-16Cycling steps.17, SUS_STAT #This signal indicates that the system enters a suspended state, the signal from the PCH claims system into a low power state,This signal can also be used for other peripheral devices to turn off the output. This signal should be in the normal starting processDriven high.18, THRMTRIP #This signal is a signal for monitoring the core temperature of the CPU, when the monitored temperature rises to the limit toAfter time, THRMTRIP # signal is driven low, PCH receive THRMTRIP # signal, it will immediatelyDrive SLP_S5 # signal is low, so that the whole system into the S5 state, close supply. Also knownSaid temperature causes power failure.PS: Before PRCOPWRGD effective, THRMTRIP # signal is negligible. Only inAfter PRCOPWRGD effective, THRMTRIP # before they can work. This signal is high under normalFlat, and only when the CPU temperature is too high may be driven low.19, PLTRST #This signal is always reset the entire platform, when SUS_STAT # is driven high 60USAfter, PLTRST # is driven high. Complete reset of the other devices and the CPU.20, DMIAfter PLTRST # is driven high, CPU and PCH via DMI bus for data exchange,Complete the boot process. Overall timing of the end.